"Evaluation of fault tolerant technique based on homogeneous FPGA architecture."

Yuki Nishitani et al. (2012)

> Home

Details and statistics

DOI: 10.1109/VLSI-SOC.2012.6379034

access: closed

type: Conference or Workshop Paper

metadata version: 2022-09-06

- view
  - electronic edition via DOI (archived)
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsi/NishitaniIAIKS12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/NishitaniIAIKS12
Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC 2012: 225-230

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.