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"Defect-aware synthesis for reconfigurable single-electron transistor arrays."

Juinn-Dar Huang, Yi-Hang Chen, Jia-Shin Lu (2017)

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DOI: 10.1109/VLSI-SOC.2017.8203487

access: closed

type: Conference or Workshop Paper

metadata version: 2020-06-15

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  - conf/vlsi/HuangCL17
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  - https://dblp.org/rec/conf/vlsi/HuangCL17
Juinn-Dar Huang, Yi-Hang Chen, Jia-Shin Lu:
Defect-aware synthesis for reconfigurable single-electron transistor arrays. VLSI-SoC 2017: 1-6

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