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"3D-LIN: A configurable low-latency interconnect for multi-core clusters ..."

Giulia Beanato et al. (2012)

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DOI: 10.1109/VLSI-SOC.2012.6379001

access: closed

type: Conference or Workshop Paper

metadata version: 2022-09-06

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  - conf/vlsi/BeanatoLMLB12
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Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini:
3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory. VLSI-SoC 2012: 30-35

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