"A Statistical Wafer Scale Error and Redundancy Analysis Simulator."

Atishay et al. (2019)

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DOI: 10.1007/978-3-030-53273-4_7

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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Atishay, Ankit Gupta, Rashmi Sonawat, Helik Kanti Thacker, Prasanth B:
A Statistical Wafer Scale Error and Redundancy Analysis Simulator. VLSI-SoC (Selected Papers) 2019: 139-163

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