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"A 6.4 Gb/s source synchronous receiver core with variable offset equalizer ..."
Kunzhi Yu et al. (2013)
- Kunzhi Yu, Xuqiang Zheng, Ke Huang, Xuan Ma, Ziqiang Wang, Chun Zhang, Zhihua Wang:
A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. VLSI-DAT 2013: 1-4
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