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"A novel power noise simulation methodology for chip design using Wafer ..."

Yipin Wu et al. (2014)

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DOI: 10.1109/VLSI-DAT.2014.6834875

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Yipin Wu, Zhigang Hao, Jingchun Han, Joy Tsai:
A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging. VLSI-DAT 2014: 1-4

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