"A high-speed dual-phase processing pipelined domino circuit design with a ..."

Ching-Hwa Cheng, Jiun-In Guo (2012)

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DOI: 10.1109/VLSI-DAT.2012.6212635

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Ching-Hwa Cheng, Jiun-In Guo:
A high-speed dual-phase processing pipelined domino circuit design with a built-in performance adjusting mechanism. VLSI-DAT 2012: 1-4

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