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"Design and Implementation of Efficient Vedic Multiplier Using Reversible ..."

P. Saravanan et al. (2012)

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DOI: 10.1007/978-3-642-31494-0_45

access: closed

type: Conference or Workshop Paper

metadata version: 2022-05-09

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  dblp key:
  - conf/vdat/SaravananCCSK12
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P. Saravanan, P. Chandrasekar, Livya Chandran, Nikilla Sriram, P. Kalpana:
Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic. VDAT 2012: 364-366

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