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"PAElib 2.0: Power&Area Aware Modeling of CMOS Digital Circuits in VHDL."

Botond Sándor Kirei, Calin Adrian Farcas, Marina Dana Topa (2020)

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DOI: 10.1109/TSP49548.2020.9163455

access: closed

type: Conference or Workshop Paper

metadata version: 2020-11-13

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  dblp key:
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Botond Sándor Kirei, Calin Adrian Farcas, Marina Dana Topa:
PAElib 2.0: Power&Area Aware Modeling of CMOS Digital Circuits in VHDL. TSP 2020: 333-336

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