"Towards Test Case Generation for Synthesizable VHDL Programs Using Model ..."

Tolga Ayav, Tugkan Tuglular, Fevzi Belli (2010)

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DOI: 10.1109/SSIRI-C.2010.22

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Tolga Ayav, Tugkan Tuglular, Fevzi Belli:
Towards Test Case Generation for Synthesizable VHDL Programs Using Model Checker. SSIRI (Companion) 2010: 46-53

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