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"FPGA Implementation of 128-Bit Fused Multiply Add Unit for Crypto Processors."

Sandeep Kakde et al. (2015)

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DOI: 10.1007/978-3-319-22915-7_8

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-15

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  - conf/sscc/KakdeMKS15
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Sandeep Kakde, Mithilesh Mahindra, Atish Khobragade, Nikit Shah:
FPGA Implementation of 128-Bit Fused Multiply Add Unit for Crypto Processors. SSCC 2015: 78-85

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