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"Implementation of a RISC-V SMT Core in an AI processor."

Hidetaro Tanaka et al. (2022)

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DOI: 10.1145/3568562.3568634

access: closed

type: Conference or Workshop Paper

metadata version: 2022-12-05

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  dblp key:
  - conf/soict/TanakaTHSTN22
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  - https://dblp.org/rec/conf/soict/TanakaTHSTN22
Hidetaro Tanaka, Tomoaki Tanaka, Ryosuke Higashi, Tsutomu Sekibe, Shuichi Takada, Hironori Nakajo:
Implementation of a RISC-V SMT Core in an AI processor. SoICT 2022: 15-22

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