"Parallelization of Simulated Annealing Algorithm for FPGA Placement and ..."

Rajesh Eswarawaka et al. (2015)

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DOI: 10.1007/978-981-10-0448-3_84

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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Rajesh Eswarawaka, Pavan Kumar Pagadala, B. Eswara Reddy, Tarun Rao:
Parallelization of Simulated Annealing Algorithm for FPGA Placement and Routing. SocProS (1) 2015: 1001-1013

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