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"Using power gating techniques in area-array SoC floorplan design."
Chi-Yi Yeh et al. (2007)
- Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu:
Using power gating techniques in area-array SoC floorplan design. SoCC 2007: 233-236
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