"Efficient Router Architecture for Trace Reduction During NoC Post-Silicon ..."

Sidhartha Sankar Rout et al. (2019)

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DOI: 10.1109/SOCC46988.2019.1570548502

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type: Conference or Workshop Paper

metadata version: 2020-05-19

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Sidhartha Sankar Rout, Suyog Bhimrao Patil, Vaibhav Ishwarlal Chaudhari, Sujay Deb:
Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation. SoCC 2019: 230-235

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