"A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, ..."

Wei-Nan Liao et al. (2013)

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DOI: 10.1109/SOCC.2013.6749670

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu:
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. SoCC 2013: 110-115

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