![](https://dblp.uni-trier.de/img/logo.ua.320x120.png)
![](https://dblp.uni-trier.de/img/dropdown.dark.16x16.png)
![](https://dblp.uni-trier.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
default search action
"Intra-chip traffic generation under autoregressive models based on time ..."
Jose Eduardo Chiarelli Bueno Filho, Jorge Luis Gonzalez Reano, Jiang Chau Wang (2016)
- Jose Eduardo Chiarelli Bueno Filho
, Jorge Luis Gonzalez Reano
, Jiang Chau Wang
:
Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation. SoCC 2016: 41-46
![](https://dblp.uni-trier.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.