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"Integrated interlayer via planning and pin assignment for 3D ICs."

Xu He et al. (2009)

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DOI: 10.1145/1572471.1572488

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/slip/HeDHG09
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  - https://dblp.org/rec/conf/slip/HeDHG09
Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto:
Integrated interlayer via planning and pin assignment for 3D ICs. SLIP 2009: 99-104

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