"A formal design methodology for synthesizing a clock signal with an ..."

Lulu Ge et al. (2015)

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DOI: 10.1109/SIPS.2015.7344975

access: closed

type: Conference or Workshop Paper

metadata version: 2025-03-03

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Lulu Ge, Chuan Zhang, Zhiwei Zhong, Xiaohu You:
A formal design methodology for synthesizing a clock signal with an arbitrary duty cycle of M/N. SiPS 2015: 1-6

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