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"Simulation-based circuit-activity estimation for FPGAs containing hard blocks."

Sean Seeley et al. (2017)

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DOI: 10.1145/3130265.3130326

access: closed

type: Conference or Workshop Paper

metadata version: 2022-12-07

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  dblp key:
  - conf/rsp/SeeleySDPK17
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  persistent URL:
  - https://dblp.org/rec/conf/rsp/SeeleySDPK17
Sean Seeley, Vidya Sankaranaryanan, Zack Deveau, Panagiotis Patros, Kenneth B. Kent:
Simulation-based circuit-activity estimation for FPGAs containing hard blocks. RSP 2017: 36-42

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