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"FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study."

Helena Krupnova, Christian Rabedaoro, Gabriele Saucier (1999)

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DOI: 10.1109/IWRSP.1999.779042

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  persistent URL:
  - https://dblp.org/rec/conf/rsp/KrupnovaRS99
Helena Krupnova, Christian Rabedaoro, Gabriele Saucier:
FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design Case Study. IEEE International Workshop on Rapid System Prototyping 1999: 128-133

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