"An efficient hardware design of SIFT algorithm using fault tolerant ..."

Chandrajit Pal et al. (2015)

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DOI: 10.1109/RETIS.2015.7232933

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-04

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Chandrajit Pal, Pabitra Das, Sudhindu Bikash Mandal, Amlan Chakrabarti, Samik Basu, Ranjan Ghosh:
An efficient hardware design of SIFT algorithm using fault tolerant reversible logic. ReTIS 2015: 514-519

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