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"Fast spiking neural network architecture for low-cost FPGA devices."

Taras Iakymchuk et al. (2012)

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DOI: 10.1109/RECOSOC.2012.6322906

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-15

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  dblp key:
  - conf/recosoc/IakymchukRFB12
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  - https://dblp.org/rec/conf/recosoc/IakymchukRFB12
Taras Iakymchuk, Alfredo Rosado, José V. Francés, Manuel Bataller:
Fast spiking neural network architecture for low-cost FPGA devices. ReCoSoC 2012: 1-6

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