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"A Hardware Optimized High Throughput LDPC Decoder Supporting 3 Tb/s in 28 ..."

Lukasz Lopacinski et al. (2022)

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DOI: 10.1109/PIMRC54779.2022.9978104

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

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Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Jesús Gutiérrez, Milos Krstic, Eckhard Grass, Rolf Kraemer:
A Hardware Optimized High Throughput LDPC Decoder Supporting 3 Tb/s in 28 nm CMOS. PIMRC 2022: 1326-1331

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