"Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk ..."

Chih-Hsiang Lin, James B. Kuo (2009)

> Home

Details and statistics

DOI: 10.1007/978-3-642-11802-9_17

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/patmos/LinK09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/patmos/LinK09
Chih-Hsiang Lin, James B. Kuo:
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique. PATMOS 2009: 127-135

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.