"Speeding up combinational synthesis in an FPGA cluster."

César Pedraza et al. (2009)

Details and statistics

DOI: 10.3233/978-1-60750-530-3-600

access: closed

type: Conference or Workshop Paper

metadata version: 2023-11-12

a service of  Schloss Dagstuhl - Leibniz Center for Informatics