![](https://dblp.uni-trier.de/img/logo.ua.320x120.png)
![](https://dblp.uni-trier.de/img/dropdown.dark.16x16.png)
![](https://dblp.uni-trier.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de/img/search.dark.16x16.png)
default search action
"FPGA Investigation on Error-Floor Performance of a Concatenated Staircase ..."
Yi Cai et al. (2018)
- Yi Cai, Weiming Wang, Weifeng Qian, Jia Xing, Kai Tao, Junjie Yin, Shihua Zhang, Ming Lei, Erkun Sun, Ke Yang, Hungchang Chien, Qun Liao, Huan Chen:
FPGA Investigation on Error-Floor Performance of a Concatenated Staircase and Hamming Code for 400G-ZR Forward Error Correction. OFC 2018: 1-3
![](https://dblp.uni-trier.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.