"Design of Low Power VLSI Architecture for Classification of Arrhythmic ..."

Meenali Janveja et al. (2021)

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DOI: 10.1109/NORCAS53631.2021.9599864

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type: Conference or Workshop Paper

metadata version: 2021-11-23

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Meenali Janveja, Mayank Tantuway, Ketan Chaudhari, Gaurav Trivedi:
Design of Low Power VLSI Architecture for Classification of Arrhythmic Beats Using DNN for Wearable Device Applications. NorCAS 2021: 1-6

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