"A Reconfigurable Analog VLSI Neural Network Chip."

Srinagesh Satyanarayana, Yannis P. Tsividis, Hans Peter Graf (1989)

> Home

Details and statistics

DOI: —

access: open

type: Conference or Workshop Paper

metadata version: 2020-03-06

- view
  - electronic edition @ nips.cc (open access)
  - electronic edition @ djvuzone.org (archived)
- export record
  dblp key:
  - conf/nips/SatyanarayanaTG89
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/nips/SatyanarayanaTG89
Srinagesh Satyanarayana, Yannis P. Tsividis, Hans Peter Graf:
A Reconfigurable Analog VLSI Neural Network Chip. NIPS 1989: 758-768

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.