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"In-memory area-efficient signal streaming processor design for binary ..."

Haruyoshi Yonekawa et al. (2017)

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DOI: 10.1109/MWSCAS.2017.8052874

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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  - conf/mwscas/YonekawaSNAUHOT17
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  - https://dblp.org/rec/conf/mwscas/YonekawaSNAUHOT17
Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura:
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS 2017: 116-119

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