"Design of a sub-picosecond-jitter delay-lock-loop for interleaved ADC ..."

John A. McNeill, Jianping Gong, Rabeeh Majidi (2013)

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DOI: 10.1109/MWSCAS.2013.6674626

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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John A. McNeill, Jianping Gong, Rabeeh Majidi:
Design of a sub-picosecond-jitter delay-lock-loop for interleaved ADC sample clock synthesis. MWSCAS 2013: 225-228

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