"Low voltage CMOS timing generator using array of digital delay lock loops."

S. Balaji, K. S. Srinivasan (2012)

> Home

Details and statistics

DOI: 10.1109/MWSCAS.2012.6292002

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/mwscas/BalajiS12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/mwscas/BalajiS12
S. Balaji, K. S. Srinivasan:
Low voltage CMOS timing generator using array of digital delay lock loops. MWSCAS 2012: 242-245

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.