"Verification of Synchronous Circuits by Symbolic Logic Simulation."

Randal E. Bryant (1989)

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DOI: 10.1007/0-387-97226-9_21

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Randal E. Bryant:
Verification of Synchronous Circuits by Symbolic Logic Simulation. Hardware Specification, Verification and Synthesis 1989: 14-24

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