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ORCID"Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor ..."
Samira Ait Bensaid et al. (2022)
- Samira Ait Bensaid, Mihail Asavoae, Farhat Thabet, Mathieu Jan:
Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs. MEMOCODE 2022: 1-8
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