"Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic ..."

Juliano C. Zanelli, Carolina Metzler, Ricardo Augusto da Luz Reis (2020)

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DOI: 10.1109/LASCAS45839.2020.9069042

access: closed

type: Conference or Workshop Paper

metadata version: 2020-05-05

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Juliano C. Zanelli, Carolina Metzler, Ricardo Augusto da Luz Reis:
Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits. LASCAS 2020: 1-4

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