Stop the war!
Остановите войну!
for scientists:
default search action
"Design and Implementation of High Speed Arithmetic Coder Architecture of ..."
M. F. Ebian, E. Elsehley, A. E. Elhenawy (2008)
- M. F. Ebian, E. Elsehley, A. E. Elhenawy:
Design and Implementation of High Speed Arithmetic Coder Architecture of JPEG2000 on Reconfigurable FPGA. IWCIA Special Track on Applications 2008: 235-241
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.