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"Block and booth floating point number multiplication algorithms in FPGA's ..."

Yulistiyan Wardhana et al. (2017)

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DOI: 10.1109/IWBIS.2017.8275105

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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  - conf/iwbis/WardhanaPSJMS17
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  - https://dblp.org/rec/conf/iwbis/WardhanaPSJMS17
Yulistiyan Wardhana, H. S. Putra, S. I. Sakinah, Wisnu Jatmiko, Petrus Mursanto, Prahesa Kusuma Setia:
Block and booth floating point number multiplication algorithms in FPGA's generalized learning vector quantization implementation. IWBIS 2017: 69-75

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