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"A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit ..."

Narumi Sakashita et al. (1996)

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DOI: 10.1109/TEST.1996.556977

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/itc/SakashitaOSSHTKKYA96
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  persistent URL:
  - https://dblp.org/rec/conf/itc/SakashitaOSSHTKKYA96
Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe:
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. ITC 1996: 319-324

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