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"Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous ..."

Benoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-Francois Cote (2008)

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DOI: 10.1109/TEST.2008.4700574

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/itc/Nadeau-DostieTC08
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  persistent URL:
  - https://dblp.org/rec/conf/itc/Nadeau-DostieTC08
Benoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-Francois Cote:
Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks. ITC 2008: 1-10

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