"A Test-Clock Reduction Method for Scan-Designed Circuits."

Jau-Shien Chang, Chen-Shang Lin (1994)

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DOI: 10.1109/TEST.1994.527967

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Jau-Shien Chang, Chen-Shang Lin:
A Test-Clock Reduction Method for Scan-Designed Circuits. ITC 1994: 331-339

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