"Capture power reduction using clock gating aware test generation."

Krishna Chakravadhanula et al. (2009)

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DOI: 10.1109/TEST.2009.5355649

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang:
Capture power reduction using clock gating aware test generation. ITC 2009: 1-9

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