"On-Line Testable Logic Desgin for FPGA Implementation."

Alfred L. Burress, Parag K. Lala (1997)

> Home

Details and statistics

DOI: 10.1109/TEST.1997.639653

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/itc/BurressL97
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/itc/BurressL97
Alfred L. Burress, Parag K. Lala:
On-Line Testable Logic Desgin for FPGA Implementation. ITC 1997: 471-478

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.