"Optimizing Post-Silicon Validation for FPGA Serial Configuration using an ..."

Mohd Amiruddin Zainol, Sompon Khamron, Ng Gua Bin (2023)

> Home

Details and statistics

DOI: 10.1109/ITC-ASIA58802.2023.10301165

access: closed

type: Conference or Workshop Paper

metadata version: 2023-11-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/itc-asia/ZainolKB23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/itc-asia/ZainolKB23
Mohd Amiruddin Zainol, Sompon Khamron, Ng Gua Bin:
Optimizing Post-Silicon Validation for FPGA Serial Configuration using an Automation Framework and Timing Characterization Verification. ITC-Asia 2023: 1-6

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.