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"An integrated design environment of fault tolerant processors with ..."

Yi-Ju Ke, Yi-Chieh Ghen, Jng-Jer Huang (2017)

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DOI: 10.1109/ITC-ASIA.2017.8097134

access: closed

type: Conference or Workshop Paper

metadata version: 2019-11-13

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  dblp key:
  - conf/itc-asia/KeGH17
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Yi-Ju Ke, Yi-Chieh Ghen, Jng-Jer Huang:
An integrated design environment of fault tolerant processors with flexible HW/SW solutions for versatile performance/cost/coverage tradeoffs. ITC-Asia 2017: 162-167

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