Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID"CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer ..."
Maher Assaad, David R. S. Cumming (2007)
- Maher Assaad
, David R. S. Cumming:
CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC. SoC 2007: 1-4
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-02-05 20:35 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
