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"A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean ..."

Xun Sun et al. (2019)

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DOI: 10.1109/ISSCC.2019.8662298

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-30

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Xun Sun, Akshat Boora, Wenbing Zhang, Venkata Rajesh Pamula, Visvesh Sathe:
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS. ISSCC 2019: 230-232

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