"A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI ..."

Anant Singh et al. (2009)

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DOI: 10.1109/ISSCC.2009.4977507

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-20

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Anant Singh, Michael Ciraula, Don Weiss, John J. Wuu, Philippe Bauser, Paul de Champs, Hamid Daghighian, David E. Fisch, Philippe Graber, Michel Bron:
A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology. ISSCC 2009: 460-461

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