"A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based ..."

Yuhwan Shin et al. (2023)

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DOI: 10.1109/ISSCC42615.2023.10067283

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

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Yuhwan Shin, Yongwoo Jo, Juyeop Kim, Junseok Lee, Jongwha Kim, Jaehyouk Choi:
A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25^%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces. ISSCC 2023: 408-409

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