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"19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based ..."

Akihide Sai et al. (2016)

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DOI: 10.1109/ISSCC.2016.7418044

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura:
19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. ISSCC 2016: 336-337

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