Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap ..."

Samir Parikh et al. (2013)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2013.6487622

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/ParikhKHJTMWKSY13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/ParikhKHJTMWKSY13
Samir Parikh, Tony Kao, Yasuo Hidaka, Jian Jiang, Asako Toda, Scott McLeod, William W. Walker, Yoichi Koyanagi, Toshiyuki Shibuya, Jun Yamada:
A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. ISSCC 2013: 28-29

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.